CNN-MERP: An FPGA-Based Memory-Efficient Reconfigurable Processor for Forward and Backward Propagation of Convolutional Neural Networks

摘要

Large-scale deep convolutional neural networks (CNNs) are widely used inmachine learning applications. While CNNs involve huge complexity, VLSI (ASICand FPGA) chips that deliver high-density integration of computationalresources are regarded as a promising platform for CNN's implementation. Atmassive parallelism of computational units, however, the external memorybandwidth, which is constrained by the pin count of the VLSI chip, becomes thesystem bottleneck. Moreover, VLSI solutions are usually regarded as a lack ofthe flexibility to be reconfigured for the various parameters of CNNs. Thispaper presents CNN-MERP to address these issues. CNN-MERP incorporates anefficient memory hierarchy that significantly reduces the bandwidthrequirements from multiple optimizations including on/off-chip data allocation,data flow optimization and data reuse. The proposed 2-level reconfigurabilityis utilized to enable fast and efficient reconfiguration, which is based on thecontrol logic and the multiboot feature of FPGA. As a result, an externalmemory bandwidth requirement of 1.94MB/GFlop is achieved, which is 55% lowerthan prior arts. Under limited DRAM bandwidth, a system throughput of1244GFlop/s is achieved at the Vertex UltraScale platform, which is 5.48 timeshigher than the state-of-the-art FPGA implementations.